1. Field of the Invention
The present invention relates to a semiconductor memory device so designed as to decrease power consumed at the time of reading data from memory cells.
2. Description of the Related Art
In general, each transistor in a semiconductor memory device such as a ROM (Read Only Memory) can store binary information, such as xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, or multi-value information which is expressed by the level of the gate voltage for turning on or off the transistor by controlling the threshold value.
The semiconductor memory device has transistors for a plurality of memory cells formed in rows and columns on a semiconductor substrate. The transistors for memory cells have gates connected to word lines formed in the row direction and drains connected to bit lines formed in the column direction.
In reading data stored in the memory cells in this semiconductor memory device, a memory cell corresponding to an input address signal is selected by a word line and a bit line which are enabled by a decoder. As the amount of the current that flows in the transistor of the selected memory cell is compared with the amount of the current that flows in a reference memory cell, data stored in the memory cell corresponding to the input address signal is read out.
In the aforementioned semiconductor memory device, each of the transistors for memory cells (hereinafter simply referred to as xe2x80x9cmemory-cell transistorsxe2x80x9d) is formed on the semiconductor substrate independently of other memory-cell transistors by a device isolation film. The drains of memory-cell transistors are connected to the associated bit lines and the sources are grounded.
While a circuit in the aforementioned semiconductor memory device, which is necessary for data reading, takes a simple structure, however, a contact for connecting a diffusion layer which forms the drain of each memory-cell transistor and the associated bit line should be formed on that diffusion layer. To form the contact in the diffusion layer of the drain, therefore, another contact should be formed, thus requiring a larger area for the diffusion layer than actually needed as a constituting element of the transistor. In other words, the structure of those memory-cell transistors stands in the way of increasing the integration level of memory cells.
As a solution to the aforementioned shortcoming of the memory-cell transistors, a virtual ground type structure and layout have been employed for memory-cell transistors in order to improve the integration level of memory cells.
Specifically, the drains and sources of memory-cell transistors adjoining in the row direction are formed by a common diffusion layer and a plurality of diffusion layers are connected in the column direction (by sub bit lines and sub virtual ground lines) so that the diffusion layers are connected in a matrix form. This makes it unnecessary to provide a contact in an area where each memory cell is to be formed. This structure can improve the integration level of memory-cell transistors as compared with the structure that needs such a contact.
To increase the reading speed of this virtual ground type semiconductor memory circuit, burst reading is carried out to read out stored data. At this time, the reading speed is improved by continuously reading multiple bits by single address setting.
Depending on the structure of a circuit in which a semiconductor memory circuit is used, however, the number of burst bytes (bits) to be read out by single address setting may vary. In this respect, a semiconductor memory circuit is so constructed as to be able to select plural types of bit quantities in burst reading.
A conventional semiconductor memory device which employs the aforementioned virtual ground type transistor structure for memory cells will now be described with reference to FIGS. 1 and 2. FIGS. 1 and 2 are block diagrams showing the structure of the aforementioned virtual ground type semiconductor memory device. In this example, the number of burst reading bits selectable is either 4 bits or 8 bits.
In FIGS. 1 and 2, data is stored in memory-cell transistors which constitute each of 16 cell plates (memory cell plates 16A0 to 16A15) of a memory cell area 16A. Each cell plate is separated into two areas corresponding to two output terminals; for example, the cell plate 16A0 is separated into two areas corresponding to an output terminal TO0 and an output terminal TO1.
That is, the cell plate 16A0 is separated into cell areas that store data to be respectively output from the output terminals TO0 and TO1. Likewise, the cell plate 16A1 is separated into cell areas that store data to be respectively output from output terminals TO2 and TO3. Likewise, each of the remaining cell plates 16A2 to 16A15 is separated into cell areas corresponding to output terminals TO4 and TO5, or output terminals TO30 and TO31.
In reading data from the aforementioned cell area of the semiconductor memory device, switching the burst output between 8 bits and 4 bits is determined how deep the cache or buffer is provided in the circuit that uses this semiconductor memory device. This bit switching is set by a control signal CSB, control signal RASB, control signal CASB and an address signal AD0 when the semiconductor memory device is used. The following will discuss this bit switching step by step.
A control signal buffer 29 shapes the waveform of an input clock enable signal CKE and changes the voltage level thereof, and outputs the resultant signal as a control signal CK to a clock control circuit 30. Likewise, the control signal buffer 29 shapes the waveform of an input clock signal CLK and changes the voltage level thereof, and outputs the resultant signal as a clock signal CL to the clock control circuit 30.
The clock control circuit 30 sends the input control clock signal CL to a counter 18 when the input control signal CK has an xe2x80x9cHxe2x80x9d level and does not send the input clock signal CL to the counter 18 when the input control signal CK has an xe2x80x9cLxe2x80x9d level.
Further, the control signal buffer 129 shapes the waveform of the input control signal CSB and changes the voltage level thereof, and outputs the resultant signal as a control signal CSBI to an instruction decoder 28. Likewise, the control signal buffer 29 shapes the waveform of the input clock signal RASB and changes the voltage level thereof, shapes the waveform of the input control signal CASB and changes the voltage level thereof, shapes the waveform of the input control signal MRB and changes the voltage level thereof, and outputs the resultant signals as control signals RASBI, CASBI and MRBI to the instruction decoder 28, respectively.
The instruction decoder 28 sends a control signal MRSB2 as an L-level signal to a switch circuit 14 when the control signals CSBI, RASBI, CASBI and MRBI all become an xe2x80x9cLxe2x80x9d level.
The switch circuit 14 sets the number of burst output bits (per one output terminal) based on the address signal AD0 and an address signal AD1 when the control signal MRSB2 input has an xe2x80x9cLxe2x80x9d level.
Specifically, in the case where the control signal MRSB2 input has an xe2x80x9cLxe2x80x9d level, the switch circuit 14 outputs a control signal MDBL8 with an xe2x80x9cHxe2x80x9d level to set the number of burst output bits to 8 bits when the address signal AD0 has an xe2x80x9cLxe2x80x9d level and the address signal AD1 has an xe2x80x9cHxe2x80x9d level, and outputs the control signal MDBL8 with an xe2x80x9cLxe2x80x9d level to set the number of burst output bits to 4 bits when the address signal AD0 has an xe2x80x9cHxe2x80x9d level and the address signal AD1 has an xe2x80x9cLxe2x80x9d level. Accordingly, the switch circuit 14 sets the number of bits sequentially output from each output terminal in the burst reading.
To specify memory-cell transistors in each of the cell plates 16A0 to 16A15 in the memory cell area 16A and read data stored in those memory-cell transistors from output terminals TO0 to TO31, for example, addresses AD0 to AD12 are input from an external CPU (Central Processing Unit) or the like.
Addresses buffer 11 shapes the waveforms of address signals AD0-AD12 and sends the resultant address signals AD0-AD12 to an address latch 12.
The address latch 12 stores the address signals AD0-AD12 input from the address buffer 11 as row address signals AD0AT, AD1AT, and AD12AT at the timing when the control signal CSB and the control signal RASB both become an xe2x80x9cLxe2x80x9d level.
The address latch 12 sends the stored row address signals AD0AT-AD12AT to an X decoder 13, the row address signals AD0AT and AD1AT to the switch circuit 14, the row address signal AD0AT to a VG decoder 15, and the row address signal AD0AT to a Y decoder 17.
The address latch 12 stores the address signals AD0-AD7 input from the address buffer 11 as column address signals AD0RT, AD1RT, . . . , and AD7RT at the timing when the control signal CSB and the control signal CASB both become an xe2x80x9cLxe2x80x9d level.
The address latch 12 sends the stored column address signals AD4RT-AD7RT to the VG decoder 15, the column address signals AD4RT, AD6RT and AD7RT to the Y decoder 17, the column address signal AD0RT-AD2RT to the counter 18 the column address signal AD2RT and AD3RT to a Y2 decoder 19, the column address signal AD4RT-AD6RT to a bank decoder 20, and the column address signal AD4RT-AD7RT to a VGPG decoder 21.
The X decoder 13 generates word line select signals corresponding to word lines WD0-WD4095 based on the row address signals AD1AT-AD12AT and sends those signals to the gates of the associated memory-cell transistors in the memory cell area 16A which are respectively connected to the word lines WD0-WD4095.
Based on the input row address signal AD0AT and column address signals AD4RT-AD7RT, the VG decoder 15 sends virtual ground control signals VG00 to VG03 to a VG selector 26A.
The Y decoder 17 generates Y selector control signals Y00 to Y07 based on the row address signal AD0AT and the column address signals AD4RT, AD6RT and AD7RT and sends those control signals to a Y selector circuit 22A.
The Y2 decoder 19 generates Y selector control signals Y20 to Y23 based on the column address signals AD2RT and AD3RT and sends those control signals to the Y selector circuit 22A.
Based on the column address signals AD4RT-AD7RT, the VGPG decoder 21 sends virtual ground control signals VG10 and VG11 and a precharge control signal PG1 to a precharge circuit 27A.
For example, the X decoder 13 decodes the row address signals AD1AT-AD12AT output from the address latch 12 and selects and enables one of the word lines WD0-WD4095. Accordingly, the memory-cell transistors in the row direction of each of the cell plates 16A0-16A15 in the memory cell area 16A are selected simultaneously to be ready for reading data.
Based on the individual control signals generated by the aforementioned Y decoder 17, Y2 decoder 19, bank decoder 20, VG decoder 15 and VGPG decoder 21, data is read out as illustrated in FIG. 3 for each of the output terminals TO0-TO31. FIG. 3 is a block diagram showing the structures of the Y selector circuit 22A, a sense amplifier circuit 23A and a latch circuit 24 per one output terminal of the semiconductor memory device, for example, a Y selector section 40A, a Y2 selector section 50, a sense amplifier section 60 and a latch section 70 which correspond to the output terminal TO0.
In this diagram, based on the input Y selector control signals Y00-Y07, Y10 and Y11, and precharge control signals P0 and P1, the Y selector section 40A selects an associated one of eight main bit lines for outputting data from the associated memory-cell transistors in the cell plate 16A0 and connects the selected main bit line to the associated data line.
Specifically, there are eight main bit lines corresponding to each of data lines D0A, D0B, D1A, D1B, D2A, D2B, D3A, D3B, D4A, D4B, D5A, D5B, D6A, D6B, D7A and D7B, and one of the eight main bit lines is selected by the Y selector section 40A to read data stored in the associated memory-cell transistors.
The Y2 selector section 50 comprises transistors M0A, M0B, M1A, M1B, M2A, M2B, M3A, M3B, M4A, M4B, M5A, M5B, M6A, M6B, M7A and M7B, which are, for example, n channel MOS transistors.
Based on the Y selector control signals Y20 and Y22 input from the Y2 decoder 19, the Y2 selector section 50 sends data on either the data line D0A or the data line D0B to a sense amplifier SA0 in the sense amplifier section 60.
Specifically, when the Y selector control signal Y20 has an xe2x80x9cHxe2x80x9d level and the Y selector control signal Y22 has an xe2x80x9cLxe2x80x9d level, the transistor M0A in the Y2 selector section 50 is turned on and the transistor M0B is turned off, so that data on the data line D0A is sent to the sense amplifier SA0.
When the Y selector control signal Y20 has an xe2x80x9cLxe2x80x9d level and the Y selector control signal Y22 has an xe2x80x9cHxe2x80x9d level, on the other hand, the transistor M0A in the Y2 selector section 50 is turned off and the transistor M0B is turned on, so that data on the data line D0B is sent to the sense amplifier SA0.
Likewise, based on the Y selector control signals Y20 and Y22 input from the Y2 decoder 19, the Y2 selector section 50 sends data on either the data line D1A or the data line D1B to a sense amplifier SA1 in the sense amplifier section 60, sends data on either the data line D2A or the data line D2B to a sense amplifier SA2 and sends data on either the data line D3A or the data line D3B to a sense amplifier SA3.
Based on the Y selector control signals Y21 and Y23 input from the Y2 decoder 19, the Y2 selector section 50 sends data on either the data line D4A or the data line D4B to a sense amplifier SA4 in the sense amplifier section 60.
Specifically, when the Y selector control signal Y21 has an xe2x80x9cHxe2x80x9d level and the Y selector control signal Y23 has an xe2x80x9cLxe2x80x9d level, the transistor M4A in the Y2 selector section 50 is turned on and the transistor M4B is turned off, so that data on the data line D4A is sent to the sense amplifier SA4.
When the Y selector control signal Y21 has an xe2x80x9cLxe2x80x9d level and the Y selector control signal Y23 has an xe2x80x9cHxe2x80x9d level, on the other hand, the transistor M4A in the Y2 selector section 50 is turned off and the transistor M4B is turned on, so that data on the data line D4B is sent to the sense amplifier SA4.
Likewise, based on the Y selector control signals Y21 and Y23 input from the Y2 decoder 19, the Y2 selector section 50 sends data on either the data line D5A or the data line D5B to a sense amplifier SA5 in the sense amplifier section 60, sends data on either the data line D6A or the data line D6B to a sense amplifier SA6 and sends data on either the data line D7A or the data line D7B to a sense amplifier SA7.
The sense amplifier section 60 comprises the sense amplifiers SA0, SA1, SA2, SA3, SA4, SA5, SA6 and SA7.
The sense amplifier SA0 determines whether data stored in each memory-cell transistor is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d by comparing data on the selected one of the data lines D0A and D0B with the reference potential of a reference signal RG from a reference cell 35, and sends the determination result to a latch 71 in the latch section 70.
Likewise, each of the sense amplifiers SA1 to SA7 determines whether data stored in each memory-cell transistor is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d by comparing data input through the transistor connected to that sense amplifier with the reference potential of the reference signal RG from the reference cell 35 (FIG. 2), and sends the determination result to an associated one of latches 72 to 78 in the latch section 70.
The latches 71-78 holds data on the determination results input from the associated sense amplifiers SA0-SA7 based on a latch signal input at a predetermined timing.
When the number of burst readout bits set in the switch circuit 14 (FIGS. 1 and 2) is xe2x80x9c8xe2x80x9d, the sense amplifiers SA0-SA7 are enabled by sense amplifier enable signals SAEB20 and SAEB21 supplied from a delay circuit 31A (FIGS. 1 and 2), and data on the results of determination made by the sense amplifiers SA0-SA7 are sent to the associated latches 71-78.
When the number of burst readout bits set in the switch circuit 14 (FIGS. 1 and 2) is xe2x80x9c4xe2x80x9d, on the other hand, either a group of the sense amplifiers SA0-SA3 or a group of the sense amplifiers SA4-SA7 are enabled based on an address signal by the sense amplifier enable signals SAEB20 and SAEB21 supplied from the delay circuit 31A (FIGS. 1 and 2), and data on the results of determination made by the sense amplifiers SA0-SA3 or data on the results of determination made by the sense amplifiers SA4-SA7 are sent to the associated latches 71-74 or the associated latches 75-78. That is, when the number of burst bits (burst length) is xe2x80x9c4xe2x80x9d, half the sense amplifiers that are not used are not enabled, thus reducing consumed power.
The latches 71-78 send the held data to a burst selector 79. When the burst length is 8 bits, the burst selector 79 sends the data input from the latches 71-78 to the output terminal TO0 in order from the latch 71 based on select signals BD0 to BD7 supplied from the burst decoder 29 (FIGS. 1 and 2).
When the burst length is 4 bits, on the other hand, the burst selector 79 sends either the data input from the latches 71-74 or the data input from the latches 75-78 to the output terminal TO0 in order based on the select signals BD0-BD7 supplied from the burst decoder 29 (FIGS. 1 and 2).
In FIGS. 1 and 2, the counter 18 performs counting based on the values of data of the column address signals AD0RT-AD2RT supplied from the address latch 12 for each input of the clock signal CL.
Further, the counter 18 performs counting between xe2x80x9c0xe2x80x9d to xe2x80x9c7xe2x80x9d when the control signal MDBL8 has an xe2x80x9cHxe2x80x9d level (in the case of the burst output of 8 bits), i.e., the counter 18 performs counting of the count value of {count signal CT2, count signal CT1, count signal CT0} from {0, 0, 0} to {1, 1, 1} for each input of the clock signal CL.
Furthermore, the counter 18 performs counting between xe2x80x9c0xe2x80x9d to xe2x80x9c3xe2x80x9d when the control signal MDBL8 has an xe2x80x9cLxe2x80x9d level and the column address signal AD2RT has an xe2x80x9cLxe2x80x9d level (in the case of the burst output of 4 bits), i.e., the counter 18 performs counting of the count value of {count signal CT2, count signal CT1, count signal CT0} from {0, 0, 0} to {0, 1, 1}. When the column address signal AD2RT has an xe2x80x9cHxe2x80x9d level, the counter 18 performs counting between xe2x80x9c4xe2x80x9d to xe2x80x9c7xe2x80x9d, i.e., the counter 18 performs counting of the count value of {count signal CT2, count signal CT1, count signal CT0} from {1, 0, 0} to {1, 1, 1}.
A burst decoder 29 outputs the select signals BD0-BD7 in accordance with the count value {count signal CT2, count signal CT1, count signal CT0} based on a truth table shown in FIG. 4. Specifically, the burst decoder 29 outputs a select signal {0, 0, 0, 0, 0, 0, 0, 1} as a select signal {select signal BD7, select signal BD6, select signal BD5, select signal BD4, select signal BD3, select signal BD2, select signal BD1, select signal BD0} when the count value is {0, 0, 0}, and outputs a select signal {1, 0, 0, 0, 0, 0, 0, 1} when the count value is {1, 1, 1}.
Accordingly, as mentioned above, the burst selector 79 in the latch circuit 24 is controlled to either the case where the burst output is 8 bits or the case where the burst output is 4 bits for each of the output terminals TO0-TO31 by the aforementioned select signal {select signal BD7, select signal BD6, select signal BD5, select signal BD4, select signal BD3, select signal BD2, select signal BD1, select signal BD0} based on the count value {count signal CT2, count signal CT1, count signal CT0} output from the counter 18.
Specifically, with the burst length being 8 bits, for example, when the select signal {0, 0, 0, 0, 0, 0, 0, 1} to the select signal {1, 0, 0, 0, 0, 0, 0, 0} are input from the burst decoder 29 (FIGS. 1 and 2) in FIG. 4, the burst selector 79 outputs the data stored in the latch 71 to the output terminal TO0 in the case of the select signal {0, 0, 0, 0, 0, 0, 0, 1} and sequentially outputs the data stored in the latches 71-78 to the output terminal TO0 in the burst length of 8 bits every time the select signal {select signal BD7, select signal BD6, select signal BD5, select signal BD4, select signal BD3, select signal BD2 select signal BD1, select signal BD0} is changed.
With the burst length being 4 bits, on the other hand, when the select signal {0, 0, 0, 0, 0, 0, 0, 1} to the select signal {0, 0, 0, 0, 1, 0, 0, 0} or the select signal {0, 0, 0, 1, 0, 0, 0,} to the select signal {1, 0, 0, 0, 0, 0, 0,0} are input from the burst decoder 29 (FIGS. 1 and 2), the burst selector 79 outputs the data stored in the latch 71 to the output terminal TO0 in the case of the select signal {0, 0, 0, 0, 0, 0, 0, 1} and sequentially outputs the data stored in the latches 71-78 to the output terminal TO0 in the burst length of 4 bits every time the select signal {select signal BD7, select signal BD6, select signal BD5, select signal BD4, select signal BD3, select signal BD2, select signal BD1, select signal BD0} is changed.
As described above, the burst length of 4 bits and the burst length of 8 bits are switched from one to the other, and in the case of the burst length of 4 bits, the sense amplifiers for the four bits which are not used are not enabled, thus reducing the power consumed accordingly.
To prevent the current from flowing in those memory-cell transistors which are not selected at the time of data reading data stored in memory-cell transistors, and thus prevents erroneous reading, however, the conventional virtual ground type semiconductor memory device is provided with the precharge circuit that prevents the current from flowing in the unselected memory-cell transistors.
To set the associated sub bit lines and sub virtual ground lines connected to the memory-cell transistors to a predetermined voltage at which the current does not flow, therefore, the sub bit lines and sub virtual ground lines should be precharged by this precharge circuit in the conventional semiconductor memory device.
This precharge current inevitably becomes large due to many memory-cell transistors connected. In the case where the burst length is 4 bits, therefore, simple disabling of the remaining four bits of each sense amplifier is insufficient to reduce the consumed power. In this case, to ensure the intended reduction of the consumed power, it is necessary to inhibit precharging of sub bit lines and sub virtual ground lines which are connected to the remaining half of the memory-cell transistors of the semiconductor memory device and are not to be accessed.
With the structure of the conventional semiconductor memory device, however, when unnecessary individual bit lines and unnecessary individual virtual ground lines are not precharged, the current flows through those memory-cell transistors which are not selected. This shortcoming will be discussed below briefly.
The data reading operation of the semiconductor memory device will be described with reference to FIGS. 12 through 15.
FIG. 12 is a conceptual diagram showing the relationship between a block BK4 which is an extracted portion of the precharge circuit 27A, VG selector 26A, cell plate 16A0, Y selector section 40A and Y2 selector section 50 that correspond to the sense amplifier SA3 in FIG. 3 and a block BK5 which is an extracted portion of the precharge circuit 27A, VG selector 26A, cell plate 16A0, Y selector section 40A and Y2 selector section 50 that correspond to the sense amplifier SA4. FIG. 13 is a block diagram showing the structure of the block BK4 in FIG. 12, and FIG. 14 is a block diagram showing the structure of the block BK5 in FIG. 12.
FIG. 15 is a block diagram showing the structure of an area Q in FIG. 12 which is extracted from the cell plate 16A0 and is the peripheral portion of a single bank block of word lines WD0-WD63 in the word lines WD0-WD4095. In an area C1 in FIG. 15 are formed memory-cell transistors which are similar to memory-cell transistors MSA0 to MSA7.
A description of the structure and operation of those other than the associated transistors and signal lines will not be given below.
Suppose that with the burst length of 8 bits, an address signal is input which selects the memory-cell transistor MSA0 as holding data to be read out to the sense amplifier SA3. At the same time, an unillustrated memory-cell transistor which is at the location corresponding to the memory-cell transistor MSA0 is selected as holding data to be read out to the sense amplifier SA4, and data is output to the sense amplifier SA4 in a process similar to what will be explained below. The following will discuss the flow of data to be read out to the sense amplifier SA3. At this time, the word line WD0 is enabled (xe2x80x9cHxe2x80x9d level) by the X decoder 13 (FIGS. 1 and 2).
Data is stored in each memory-cell transistor by changing the threshold voltage that controls the ON/OFF action of that transistor. That is, when each memory-cell transistor is turned on as the word line that is connected to the gate of that memory-cell transistor is enabled by changing the threshold voltage, the current that corresponding to the threshold voltage flows through the memory-cell transistor, thus causing the transistor to store data. In the case of binary data, two threshold values respectively for the state where the current is hard to flow and the state where the current is easy to flow are to be controlled.
To permit the read current from a main bit line D314 to flow only through the memory-cell transistor MSA0 to be selected, therefore, it is necessary to set a main bit line D313 in an open state (high-impedance state), a main virtual ground line VG37 at the ground potential (GND level), a main bit line D315 at a predetermined potential (precharge potential), a main bit line D40 in an open state, a main virtual ground line VG40 at the precharge potential and a main bit line D41 in an open state.
At this time, to read data on the main bit line D314 to the sense amplifier SA3, the Y selector control signals Y20 and Y21 are set to an xe2x80x9cLxe2x80x9d level and the Y selector control signals Y22 and Y23 are set to an xe2x80x9cHxe2x80x9d level. Note that the transistors M3A, M4A, M3B and M4B are n channel transistors.
Accordingly, the transistors M3B and M4B are turned on and the transistors M3A and M4A are turned off.
Further, the precharge signal P0 and Y selector controls signals Y11 become an xe2x80x9cLxe2x80x9d level and the precharge signal P1 and Y selector control signal Y10 become an xe2x80x9cHxe2x80x9d level. Note that the transistors MA10, MA11, MA0, MA1, MB10, MB11, MB0 and MB1 are n channel transistors.
Accordingly, the transistors MA10, MA1, MB10 and MB1 are turned on and the transistors MA11, MA0, MB11 and MB0 are turned off.
Further, the Y decoder 17 (FIGS. 1 and 2) sets the Y selector control signals Y00 to Y05 to an xe2x80x9cLxe2x80x9d level and sets the Y selector control signals Y06 and Y07 to an xe2x80x9cHxe2x80x9d level. Note that the transistors M200 to M207 and M210 to M217 in the Y selector section 40A are n channel MOS transistors.
Accordingly, the transistors M206, M207, M216 and M217 are turned on and the transistors M200-M205 and M210-M215 are turned off.
Further, the virtual ground control signal VG10 and the precharge control signal PG1 are at an xe2x80x9cLxe2x80x9d level and the virtual ground control signal VG11 and the precharge control signal PG0 are at an xe2x80x9cHxe2x80x9d level. Note that the transistors MA50, MA51, MA60, MA61, MB50, MB51, MB60 and MB61 in the precharge circuit 27A are n channel MOS transistors.
Accordingly, the transistors MA51, MA60, MB51 and MB60 are turned on and the transistors MA50, MA61, MB50 and MB61 are turned off.
Furthermore, the virtual ground control signals VG00 and VG03 become an xe2x80x9cHxe2x80x9d level and the virtual ground control signals VG01 and VG02 become an xe2x80x9cLxe2x80x9d level. Note that the transistors MA70 to MA73 and MB70 to MB73 are n channel MOS transistors.
Accordingly, the transistors MA70, MA73, MB70 and MB73 in the VG selector 26A are turned off and the transistors MA71, MA72, MB71 and MB72 are turned on.
Under the above-described control of the individual transistors, in the semiconductor memory device, the main bit line D314 is set at a predetermined read potential, the main bit line D313 is set to an open state (high-impedance state), the main virtual ground line VG37 is set at the ground potential (GND level), the main bit line D315 is set at a predetermined potential (precharge potential), the main bit line D40 is set in an open state, the main virtual ground line VG40 is set at the precharge potential, and the main bit line D41 is set in an open state.
Then, a select signal BSD0 to be input to a bank selector 80A from the bank decoder 20 becomes an xe2x80x9cLxe2x80x9d level, a select signal BSD1 becomes an xe2x80x9cHxe2x80x9d level, a select signal BSG0 becomes an xe2x80x9cHxe2x80x9d level, and select signals BSG1 to BSG3 become an xe2x80x9cLxe2x80x9d level. Note that transistors M100 to M111 and M120 to M131 in the bank selector 80A are n channel MOS transistors.
Accordingly, the transistors M100, M102, M104, M106, M108, M110, M120, M124 and M128 are turned on and the transistors M101, M103, M105, M107, M109, M111, M121-M123, M125-M127 and M129-M131 are turned off.
As a result of the above, a sub bit line B314a, which is connected via the transistor M104 to the main bit line D314 connected to the sense amplifier SA3, and a sub virtual ground line G37a, which is connected via the transistor M124 to the main virtual ground line VG37 connected to the ground line, are connected to the memory-cell transistor MSA0, so that the current flows from the sense amplifier SA3 to the main virtual ground line VG37 via the memory-cell transistor MSA0.
The sense amplifier SA3 compares the value of the current that flows across the main bit line D314 with the current value of the reference signal RG input from the reference cell 35. When the value ofthe current flowing across the main bit line D314 is larger than the current value of the reference signal RG, for example, the threshold value is low and the memory-cell transistor is on, so that the current is flowing through the memory-cell transistor. Therefore, the sense amplifier SA3 determines that data stored in the memory-cell transistor is xe2x80x9cLxe2x80x9d.
When the value of the current flowing across the main bit line D314 is smaller than the current value of the reference signal RG, on the other hand, the threshold value is high and the memory-cell transistor is off, so that the current is not flowing through the memory-cell transistor. Therefore, the sense amplifier SA3 determines that data stored in the memory-cell transistor is xe2x80x9cHxe2x80x9d.
The reference cell 35 is constructed by a circuit which outputs the reference signal RG whose current value is, for example, an intermediate value between the voltage level of a bit signal in the case where data stored in memory-cell transistors in the memory cell section 16A is xe2x80x9cHxe2x80x9d and the voltage level of a bit signal in the case where data stored in memory-cell transistors is xe2x80x9cLxe2x80x9d.
The reference cell 35 may be constructed by a reference transistor which outputs the reference signal RG whose current value is determined by the current flowing across a selected word line and is controlled to a threshold value that becomes an intermediate voltage level between the voltage level of a bit signal in the case where data stored in the memory-cell transistors is xe2x80x9cHxe2x80x9d and the voltage level of a bit signal in the case where data stored in memory-cell transistors is xe2x80x9cLxe2x80x9d.
Even if the memory-cell transistors on the left-hand side of the memory-cell transistor MSA0 in FIG. 15 has a low threshold voltage and is in such a state where the current easily flows at this time, the associated main bit lines D312 and D313 and the main virtual ground line VG36 are in an open state so that the currents from the memory-cell transistors on the left side to the memory-cell transistor MSA0 do not adversely affect the current that flows across the sub virtual ground line G37a. That is, the amount of the current flowing toward the sub virtual ground line G37a via the memory-cell transistor MSA0 is inhibited from being restricted by the current that flows toward the sub virtual ground line G37a from the other memory-cell transistors on the left side to the memory-cell transistor MSA0, thus preventing erroneous reading.
Even if the memory-cell transistors MSA1-MSA7 on the right-hand side of the memory-cell transistor MSA0 have low threshold voltages and are in such a state where the current easily flows, the associated main bit line D315 and the main virtual ground line VG40 are at the precharge potential. This prevents the current from flowing toward the other memory-cell transistors, including the memory-cell transistors MSA1-MSA7, than the selected one.
Accordingly, when the threshold value of the memory-cell transistor MSA0 is high, the current from the sense amplifier does not flow across the sub virtual ground line G337a. If the sub virtual ground line G337a is not precharged, however, the current flows toward the other memory-cell transistors, including the memory-cell transistors MSA1-MSA7, than the selected one. Therefore, the current flows across the main bit line D315 so that the sense amplifier SA3 makes a similar decision to the one in the case where the current flows in the memory-cell transistor MSA0 and thus does erroneous reading. The precharge circuit therefore prevents such erroneous reading.
At this time, precharge circuits MP1 and MP2 precharge the associated main bit lines based on a precharge control signal PCM output from the delay circuit 31A at the timing at which the sense amplifier circuit 23A reads out data.
Likewise, precharge circuits SP1 and SP2 precharge the associated main virtual ground lines based on a precharge control signal PCS output from the delay circuit 31A at the timing at which the sense amplifier circuit 23A reads out data.
Referring to FIGS. 1 and 2, precharge control signals PCS20, PCS21, PCM20 and PCM21 are used in one embodiment of this invention and are not output from the delay circuit 31A in the prior art.
In the above-described case, in the case of the burst length of 4 bits as in the case of the burst length of 8 bits, precharging is performed on the main bit lines and main virtual ground lines which correspond to the memory-cell transistors that are not sensed by a sense amplifier.
With the burst length of 4 bits, in the case where data in the memory-cell transistors corresponding to the sense amplifiers SA0-SA3 are read out and data in the memory-cell transistors corresponding to the sense amplifiers SA4-SA7 are not read out, erroneous reading similar to the one described in the previous description of the case of the 8-bit burst length if precharging the main bit lines and main virtual ground lines which correspond to the sense amplifiers SA0-SA7 is stopped to reduce the consumed current.
Accordingly, it is an object of the present invention to provide a virtual ground type semiconductor memory device which, in the case of the burst length of 4 bits (in the case of changing the burst length), does not precharge the main bit lines and main virtual ground lines that correspond to those sense amplifiers which are not used, without causing erroneous reading, thus reducing the consumed power (consumed current) in a reading operation.
To achieve the above object, according to this invention, there is provided a semiconductor memory device which comprises a plurality of first memory cells each located at an intersection of each of a plurality of word lines and an associated one of a plurality of bit lines and each having one end connected to the associated bit line; a plurality of memory cell blocks each comprising a predetermined number of first memory cells in the plurality of the first memory cells; dummy cell blocks, provided among the memory cell blocks, for electrically isolating those memory cell blocks which are located at both ends from each other, each of the dummy cell blocks comprising second memory cells; main bit lines each provided for each of the memory cell blocks and each of the dummy cell blocks and each connected to an associated one of the bit lines; a main-bit-line control section for performing such control as to apply a predetermined voltage to the main bit lines, connect the main bit lines to associated sense amplifiers or set the main bit lines in an open state based on an address signal; virtual ground lines connected to other terminals of the first memory cells and the second memory cells; main virtual ground lines each provided for each of the memory cell blocks and each of the dummy cell blocks and each connected to an associated one of the virtual ground lines; and a main-virtual-ground-line control section for performing such control as to apply a predetermined voltage to the main virtual ground lines or set the main virtual ground lines in an open state based on an address signal.
According to a first preferable mode, in the semiconductor memory device, the second memory cells constituting the dummy cell blocks may be similar to the first memory cells in the memory cell blocks.
According to a second preferable mode, in the semiconductor memory device and the first preferable mode, each of the first memory cells may be comprised of an MOS transistor and may store data as a threshold voltage for controlling an ON/OFF state of the transistor is changed.
According to a third preferable mode, in the semiconductor memory device and the first and second preferable modes, a threshold voltage of MOS transistors constituting the second memory cells of the dummy cell blocks may be controlled to such a value that the MOS transistors are not turned on by a predetermined voltage to be applied to gates of the MOS transistors via the word lines.
According to a fourth preferable mode, in any of the semiconductor memory device and the first to third preferable modes, each of the bit lines may be connected to an associated one of the main bit lines via a first MOS transistor and each of the virtual ground lines may be connected to an associated one of the main virtual ground lines via a second MOS transistor.
According to a fifth preferable mode, in the fourth preferable mode, a threshold voltage of the first MOS transistors provided between the bit lines and the main bit lines in the dummy cell blocks may be controlled to such a value that the first MOS transistors are not turned on by a voltage of a predetermined control signal.
According to a sixth preferable mode, in the fourth or fifth preferable mode, a threshold voltage of the second MOS transistors provided between the virtual ground lines and the main virtual ground lines in the dummy cell blocks may be controlled to such a value that the second MOS transistors are not turned on by a voltage of a predetermined control signal.
According to a seventh preferable mode, the semiconductor memory device of any one of the fourth to sixth preferable modes may further comprise a memory-cell selection control section for performing ON/OFF control of the first MOS transistors and the second MOS transistors based on an input address signal to thereby select a memory cell corresponding to the address signal and control a direction of a current flowing in the memory cell in association with voltage states of the main bit lines and the main virtual ground lines.
According to an eighth preferable mode, in any of the above-described semiconductor memory devices, interconnection patterns of the main bit lines and the main virtual ground lines may be formed alternately.